Floating gate isolation and method of making the same

ABSTRACT

The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate ( 10 ), each device having a floating gate ( 36 ), comprising: first forming isolation zones ( 14 ) in the substrate ( 10 ), thereafter forming a floating gate separator ( 32 ) on the isolation zones ( 14 ) at locations where separations between adjacent floating gates ( 36 ) are to be formed, after forming the floating gate separator ( 32 ), forming the floating gates ( 36 ) on the substrate ( 10 ) between parts of the floating gate separator ( 32 ), and thereafter removing the floating gate separator ( 32 ) so as to obtain slits in between neighboring floating gates ( 36 ). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur. Furthermore, the gate profile is damaged less than in prior art slit processing methods.

The present invention relates to a method for forming a set of floatinggates (FG) which are isolated from each other by means of slits, as wellas semiconductor devices using the floating gate. The FGs are useful inthe manufacture of ultra high-density non-volatile memories (NVWM). Someexamples of NVMs include an EPROM, an EEPROM and a flash memory cell.

NVMs are used in a wide variety of commercial and military electronicdevices and equipment, such as, for example, hand-held telephones,radios and digital cameras. The market for these electronic devicescontinues to require devices with a lower voltage, lower powerconsumption and a decreased chip size.

Flash memories or flash memory cells conventionally comprise a MOSFETwith a (or a plurality of) floating gate(s) between a control gate (CG)and a channel region, the FGs and the CG being separated by a thindielectric layer. With the improvement of fabrication technologies, theFG size and the space between FGs has been reduced to sub-micrometerscale. These devices are basically miniature EEPROM cells in whichelectrons (or holes) are injected through an oxide barrier into a FG.Charges stored in the FG modify the device threshold voltage. In thisway, data is stored. The CG controls the FG. The FG to CG couplingratio, which is related to the areal overlap between the FG and the CG,affects the read/write speed of the flash memory. Furthermore, thebetter the coupling ratio, the more the required operation voltage ofthe memory cell can be reduced.

Stacked gate technology is applied in the fabrication of modem NVM cellswith very high density, as shown in FIG. 1. In a stacked gatetechnology, the CG 2 and the FG 4 are etched in a self-aligned manner inone and the same patterning step, in a direction perpendicular to theview of FIG. 1. FIG. 1 shows a cross-section in a direction along a wordline of the NVM cell. It is shown that FGs 4 are located apart from eachother to assure isolation of the FGs 4 in this direction. This isachieved by etching FG slits 6 in the bottom polysilicon gate (FG) priorto depositing an interpoly dielectric (IPD) 8 and a CG polysiliconlayer. The slits 6 can either be continuous lines (long slits) in adirection perpendicular to the plane of the paper, or separated smallslits (short slit openings). The slits 6 are etched into the Gpolysilicon to isolate adjacent FGs 4. The slit etch should be verystraight, otherwise olysilicon short between different FGs 4 can occur.These polysilicon shorts cause serious reliability problems for the NVM.

The contribution of the potential on the CG 2, VcG, to the potential onthe FG 4, V_(FG), in a non-volatile memory (NVM) cell, is determined bythe FG to CG coupling ratio, α_(FC):V _(FG)=α_(FC) ×V _(CG)

The FG to CG coupling ratio is determined by:α_(FC) =C _(FC) /C _(tot)where C_(FC) if the capacitance between FG 4 and CG 2, and

C_(tot) is the total capacitance of the FG 4.

In order to achieve maximum FG to CG coupling, the capacitance C_(FC)between FG 4 and CG 2 must be maximized, and/or the total capacitance ofthe FG 4 must be minimized.

One solution for improving the FG to CG coupling ratio is to increasethe dimensions of the FG 4, thus increasing the overlap area of the CGover the FG in the X-direction in FIG. 1, so as to increase thecapacitance C_(FC). This, however, limits the ability to reduce the cellsize and thus impedes device density improvements. Maximum densityrequires minimum spaces between FGs 4, or thus minimum width of slits 6.Slit dimensions are presently limited by lithographic processes used inmanufacturing the gate stacks.

A problem with down scaling of NVMs with polysilicon FG 4 is formed bythe small slits 6, which are the separation between adjacent FGs 4.These slits 6 become very small due to the fact that the couplingbetween FG 4 and CG 2 should remain constant with scaling. And in fact,an increase in coupling would even be better, because this reduces theprogram and erase voltages needed, and thus reduces power consumption.One way to obtain a higher coupling, is to decrease the size (width) ofthe slits 6.

It is known from U.S. Pat. No. 6,214,667 to make small slits by usingnitride (Si₃N₄) spacers next to the FGs. In this technique, slits areetched in a (relative thick) nitride layer on top of the FGs. Next,nitride sidewall spacers are formed. The nitride layer including spacersfunctions as a hard mask for the FG slit etch. A disadvantage of thismethod is the removal of the nitride, for example with H₃PO₄ phosphoricacid that etches (especially doped) polysilicon. This requires atrade-off between leaving behind nitride residues and causing a rough FGsurface. Both situations will lead to inter-poly dielectric (IPD)reliability problems.

It is an object of the present invention to provide an array of floatinggate semiconductor devices which are isolated from each other, in which,during isolation of the floating gates from each other, less damage tothe gate profile is applied, and in which, after isolating the floatinggates from each other, less residues of floating gate material or gatematerial shorts between adjacent floating gates are present.

The above objective is accomplished by a method and device according tothe present invention.

The present invention provides a method for manufacturing an array ofsemiconductor devices on a substrate, each device having a floatinggate, comprising:

-   first forming isolation zones in the substrate,-   thereafter forming a floating gate separator on the isolation zones    at locations where separations between adjacent floating gates are    to be formed,-   after forming the floating gate separator, forming the floating    gates on the substrate between parts of the floating gate separator,    and-   thereafter removing the floating gate separator so as to obtain    slits in between neighboring floating gates.

This method has an advantage over prior art in that less residues offloating gate material, e.g. polysilicon residues, or less floating gatematerial shorts between adjacent floating gates occur. Furthermore, thegate profile is damaged less than in prior art slit processing methods.

A method according to the present invention may furthermore comprise,after forming of the floating gate separator and before forming of thefloating gate, reducing the dimensions of the floating gate separator.This way, smaller slits are obtained in an easy way. The dimensions ofthe floating gate separator may be reduced to sub-lithographicdimensions, whereby dimensions depend on technology node and on processconditions. For example for 90 mn generations and beyond, the dimensionsof the floating gate separator may reduced to between 100 nm and 40 nm.

In the case of reduction of the dimensions of the floating gateseparator to sub-lithographic dimensions, slits smaller than the minimumlithographic critical dimension are obtained, which increases the FG/CGcoupling of the device obtained

The dimensions of the floating gate separator may be reduced bylithographic techniques such as resist shrink, which is a reliable andvery cheap method, and phase-shift lithography. Alternatively, thedimensions of the floating gate separator may be reduced by trim plasmaetching or by an isotropic over-etch of the floating gate separator. Theover-etch is only done after floating gate separator formation.

The floating gate separator may comprise nitride material, which allowsa selective etching to be done when removing the floating gateseparator. The floating gate separator may comprise at least two layersof different material, such as for example oxide and nitride. Thislatter solution gives less problems with degradation of highly dopedfloating gate material, e.g. highly doped polysilicon, when removing thefloating gate separator.

The method according to the present invention may furthermore compriseforming a control gate on top of the floating gates, so as to form adevice which can be used in NVMs.

According to an embodiment of the present invention, spacers may beformed next to the floating gate separator before forming the floatinggates. This way, a sharp tip of floating gate material, e.g.polysilicon, can be obtained in the FG, which is useful for poly-polyerase. With a sharp tip is meant that tangents to the upper, flatsurface of the floating gate, and the portion of the upstanding wall ofthe floating gate where it is adjacent the upper surface, include anangle of less than 90 degrees, preferably less than 70 degrees, stillmore preferred less than 50 degrees.

The forming of the floating gates may comprises removing floating gatematerial by chemical-mechanical polishing. This way, a flat FG surfaceis obtained, which is advantageous for the reliability of the memoryformed using this FG.

A method according to the present invention may furthermore comprise,after removing the floating gate separator, doping the floating gates.

The present invention also provides an array of semiconductor deviceswith a floating-gate to control-gate coupling ratio, comprising:

-   a substrate with a planar surface,-   an isolation zone in the substrate in the planar surface,-   at least two floating gates extending on the substrate in a first    direction, each floating gate partially overlapping the isolation    zone and comprising floating gate material, such as e.g.    polysilicon,-   a slit between the two floating gates, and-   a control gate extending laterally with respect to the planar    surface over the floating gates,    -   wherein at least one of the floating gates is provided with a        sharp tip of floating gate material both in the first direction        and in a second direction including an angle with the first        direction. his second direction may be perpendicular to the        first direction. With a sharp tip is meant that tangents to the        upper, flat surface of the floating gate, and the portion of the        upstanding wall of the floating gate where it is adjacent the        upper surface, include an angle of less than 90 degrees,        preferably less than 70 degrees, still more preferred less than        50 degrees.

In an array of semiconductor devices according to the present invention,the slit between two adjacent floating gates may be asub-lithographically dimensioned slit. This is advantageous for thefloating-gate to control-gate coupling ratio.

The floating gate may have a flat top surface, which is advantageous forthe reliability of a memory formed using this FG.

The present invention also provides a non-volatile memory including anarray of semiconductor devices according to the present invention. Thememory may be a flash memory or an EEPROM for example.

These and other characteristics, features and advantages of the presentinvention will become apparent from the following detailed description,taken in conjunction with the accompanying drawings, which illustrate,by way of example, the principles of the invention. This description isgiven for the sake of example only, without limiting the scope of theinvention. The reference figures quoted below refer to the attacheddrawings.

FIG. 1 shows a cross-section of a prior art NVM cell, in a directionalong a word line.

FIG. 2 shows a cross-section of a substrate provided with isolationzones and sacrificial oxide.

FIG. 3 shows the cross-section of FIG. 2 after formation of a layer ofsacrificial floating gate separation material with on top thereof afloating gate separator resist, according to a first embodiment of thepresent invention.

FIG. 4 shows a cross-section after floating gate separation materialetch, stripping of the floating gate separator resist and formation oftunnel oxide according to an embodiment of the present invention.

FIG. 5 shows the cross-section of FIG. 4 after FG polysilicondeposition.

FIG. 6 shows the cross-section of FIG. 5 after polysilicon CMP.

FIG. 7 shows the cross-section of FIG. 6 after IPD and CG formation.

FIG. 8 illustrates an FG/CG stack in a cross-section perpendicular tothe one of FIG. 7.

FIG. 9 illustrates, in cross-section, the formation of spacers next tothe floating gate separator, according to a second embodiment of thepresent invention.

FIG. 10 is the cross-section of FIG. 9 after formation of FG.

FIG. 11 is the cross-section of FIG. 10 after IPD and CG formation.

FIG. 12 is a cross-section perpendicular to the cross-section of FIG. 9,according to a third embodiment of the present invention.

FIG. 13 is the cross-section of FIG. 12 after FG, IPD and CG formation.

In the different drawings, the same reference figures refer to the sameor analogous elements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. Where the term “comprising” is used in thepresent description and claims, it does not exclude other elements orsteps. Where an indefinite or definite article is used when referring toa singular noun e.g. “a” or “an”, “the”, this includes a plural of thatnoun unless something else is specifically stated.

Furthermore, the terms top, bottom, over, under and the like in thedescription and the claims are used for descriptive purposes and notnecessarily for describing relative positions. It is to be understoodthat the terms so used are interchangeable under appropriatecircumstances and that the embodiments of the invention described hereinare capable of operation in other orientations than described orillustrated herein.

According to the present invention, in a first step, a substrate 10 or awell in a substrate is provided. In embodiments of the presentinvention, the term “substrate” may include any underlying material ormaterials that may be used, or upon which a device, a circuit or anepitaxial layer may be formed. In other alternative embodiments, this“substrate” may include a semiconductor substrate such as e.g. a dopedsilicon, a gallium arsenide (GaAs), a gallium arsenide phosphide(GaAsP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The“substrate” may include for example, an insulating layer such as a SiO₂or an Si₃N₄ layer in addition to a semiconductor substrate portion.Thus, the term substrate also includes silicon-on-glass, silicon-onsapphire substrates. The term “substrate” is thus used to definegenerally the elements for layers that underlie a layer or portions ofinterest. Also, the “substrate” may be any other base on which a layeris formed, for example a glass or metal layer. In the followingprocessing will mainly be described with reference to silicon processingbut the skilled person-will appreciate that the present invention may beimplemented based on other semiconductor material systems and that theskilled person can select suitable materials as equivalents of thedielectric and conductive materials described below.

As shown in FIG. 2, this well or substrate 10 has a surface 12 and isprovided with isolation zones such as shallow trench isolation (STI)zones 14 or thermally grown field oxide (LOCOS) regions, in order toisolate subsequent (as seen in the X-direction as defined in FIG. 1)memory cells from each other. Between two STI or LOCOS isolation zones14, the remaining substrate 10 will form an active area 16.

STI isolation zones 14 may be formed by initially creating a shallowtrench in semiconductor substrate 10, e.g. by a conventionalphotolithographic and anisotropic dry etch process such as a reactiveion etching (RIE) procedure, using e.g. C1 ₂ as etchant. The shallowtrench is created to a depth of for example between about 200 to 600 nmin the semiconductor substrate 10. After removal of the photoresistpattern, used for shallow trench definition, by plasma oxygen ashing andcareful wet cleans, a silicon oxide layer is deposited, for example by alow pressure chemical vapor deposition (LPCVD) procedure or by a plasmaenhanced chemical vapor deposition (PECVD) procedure, to a thicknessbetween about 300 to 1500 nm. The shallow trenches are thus completelyfilled. Removal of the silicon oxide from regions other than inside theshallow trenches is accomplished using either a chemical mechanicalpolishing (CMP) procedure, or via a RIE procedure using a suitableetchant, resulting in insulator filled STI regions 14.

Depending on the procedure used, the shallow trench isolation can giverise to topographic unevenness 18 next to the active area 16. Thisunevenness 18 is formed during the etch back of the oxide (HF dip) tolevel the oxide in the trench to the same height as the active areas 16.When a memory stack, comprising FG and CG, is deposited on such an STItopography with unevenness 18, this topography remains through the wholestack due to conformal deposition of gate material, e.g. polysiliconlayers. This can introduce etch problems further in the processing ofnon-volatile memories.

If instead of STI zones 14, LOCOS regions are used, they may be formedvia initially forming an oxidation resistant mask, such as siliconnitride, then exposing regions of the semiconductor substrate 10 notprotected by the silicon nitride masking pattern, to a thermal oxidationprocedure. LOCOS regions are thus created at a thickness equal to thedepth of STI zones 14. After formation of the LOCOS region, theoxidation resistant mask is removed.

STI zones 14 are preferred over LOCOS regions as they can be formed in asmaller dimension than that of the LOCOS regions, which allows thereduction of the cell dimensions, so that cell density can be increasedFurthermore, LOCOS has much more topographic unevenness than STI andwill introduce some constraints on the floating gate material thickness.Therefore, in the following description, only STI zones 14 are furtherconsidered, but it should be understood that the present inventionincludes the process steps described below carried out with LOCOSregions.

As shown in FIG. 2, on top of the substrate 10 provided with STI zones14, an insulating layer, e.g. a sacrificial oxide layer 20, comprisinge.g. silicon dioxide, is formed, preferably by thermally growing it inan oxygen-steam ambient, at a temperature between about 600 to 1000° C.,to a thickness between about 6 to 15 nm. Alternatively Rapid ThermalOxidation (RTO) with in-situ steam generation (ISSG) can be used toobtain the sacrificial oxide layer 20.

According to the present invention, after STI processing as shown inFIG. 2, a thick layer 22 of sacrificial floating gate separationmaterial is deposited on top of the insulating sacrificial oxide 20.This layer 22 of sacrificial floating gate separation material is alayer which can be selectively removed, without removing any (or asignificant amount) of the oxide present (neither STI 14 nor sacrificialoxide 20). The layer 22 of sacrificial floating gate separation materialmay, for example, be a thick layer of nitride, as shown in FIG. 3.Alternatively, the layer 22 of sacrificial floating gate separationmaterial may for example consist of two layers, e.g. a thin layer ofnitride with on top thereof a thick layer of oxide, whereby the thinlayer of nitride will function as a stopping layer when later onremoving the thick layer of oxide. The latter approach can provideadvantages for the removal at the end of the processing, as explainedlater on. The thick layer 22 of sacrificial floating gate separationmaterial preferably has the same thickness as the FG 36 which is to beformed on a later stage in the processing.

An etch mask, preferably a sub-lithographic dimensioned etch mask, iscreated, e.g. using a resist layer. This is applied on top of the thicklayer 22 of sacrificial floating gate separation material, and someparts thereof (depending on the desired pattern) are exposed, so as topattern the resist by a common exposure step. Subsequently, thenon-exposed parts (or the exposed parts, depending on the kind of resistused) are washed away, leaving behind a certain pattern of resist,allowing layers not covered by the remaining resist layer to be etchedaway. A floating gate separator resist 24 is obtained, as shown in FIG.3. The floating gate separator resist 24 is the inverse of the slit maskwith the same function in “standard” flash processing. It is a maskwhich covers locations where slits are to be formed, and which leavesother locations free. The floating gate separator resist 24 can be atminimum critical dimensions (CD).

After development of the resist layer, the size of the floating gateseparator resist 24 may be reduced, e.g. by using resist shrink (UVbake) or resist ash (trim plasma etching by means of O₂ plasma). If thefloating gate separator resist 24 was developed having a minimal CD,then after reduction it has sub-lithographic dimensions. Especially theresist shrink is a reliable and very economic and easy way to getsub-lithographic dimensions. The CD can be reduced with this techniqueby about 30-50 nm. Of course smaller dimensions can also be obtained byphase-shift lithography.

The thick layer 22 of sacrificial floating gate separation material isthen etched, using the exposed and developed and possibly reducedfloating gate separator resist 24. If the thick layer 22 of sacrificialfloating gate separation material comprises one material, such as e.g.nitride, this nitride is etched with end point on oxide (STI 14 andsacrificial oxide 20). The floating gate separator resist 24 isstripped. A floating gate separator 32 is obtained. The result is shownin FIG. 4. If the thick layer 22 of sacrificial floating gate separationmaterial consists of e.g. a thick layer of oxide on top of a thin layerof nitride, first the oxide is etched using the floating gate separatorresist 24, and thereafter the nitride layer is removed with etch stop onoxide 14, 20. Here also, the resist 24 is stripped. A floating gateseparator 32 is obtained.

Another option to reduce dimensions of the floating gate separator 32can be a short anisotropic over-etch after the etch of the layer ofsacrificial floating gate separation material, a nitride etch in theexample given (i.e. after the result shown in FIG. 4). Alternatively,instead of an anisotropic nitride etch a more isotropic nitride etch canbe used. This introduces a tapered profile instead of a straight nitrideslope. This tapering cannot cause any polysilicon shorts betweendifferent floating polysilicon gates 36. With a standard slit etch(prior art), polysilicon shorts are between adjacent floating gates 36causing a reliability problem.

In principle after dry nitride etch and stripping of the floating gateseparator resist 24, also a short wet nitride etch (isotropic) can beused to reduce the CD.

All the above options can be used to decrease the CD. The options can beperformed separately or in any combination. Except for phase-shiftlithography, the mentioned ways of doing CD reduction cannot be donewith standard slit processing.

During floating gate separator 32 formation, the removal of thesacrificial floating gate separation material, e.g. nitride, will damagethe sacrificial oxide 20. After the floating gate separator 32formation, the sacrificial oxide 20 (or the remainder of this oxide) canbe dipped away, e.g. with HF, and tunnel oxide 33 can be provided, forexample by growing it.

A next step, after having obtained the tunnel oxide 33, is the formationof FG material, e.g. deposition of the FG polysilicon 34, as shown inFIG. 5. On top of the tunnel oxide 33 and over the floating gateseparator 32, a first polysilicon layer 34 is deposited, which willlater on form the FGs 36. The deposition of the first polysilicon layer34 is preferably done by a CVD procedure, to a thickness between about50 to 400 nm. Doping of the polysilicon layer 34 is either accomplishedin situ, during deposition, e.g. via the addition of arsine or phosphineto a silane ambient, or via an ion implantation procedure, using forexample arsenic, phosphorous or boron ions applied to an intrinsicpolysilicon layer.

As is shown in FIG. 5, the polysilicon deposition follows the topographyof the wafer (also the STI topography). Next, according to the presentinvention, the polysilicon layer 34 is processed, e.g. polished down, tothe same height as the floating gate separator 32, e.g. by polysiliconchemical mechanical polishing (CMP). All unwanted topography is removedafter polysilicon CMP, and FGs are formed, as shown in FIG. 6. Thispolysilicon CMP step should be selective towards the top material of thefloating gate separator 32, in the examples given either nitride for thethick nitride layer, or oxide for the combined oxide/nitride layer. Dueto the polysilicon CMP step, the top of the FG 36 is very flat and thisis advantageous for the reliability of the memory. Prior art FGpolysilicon can have sharp grain boundaries on top, with associatedreliability problems (charge leakage).

The floating gate separator 32 is then removed. The nitride of thefloating gate separator 32 can be e.g. etched away with a wet etch.This, however, can cause problems with highly doped polysilicon of theFG 36. For this reason, instead of nitride, a double layer of nitrideand oxide may be used and is usually preferred. If a thin nitride layerand a thick oxide layer are deposited instead of the thick nitridelayer, then after the polysilicon-CMP step, first the oxide can beetched away by means of a wet etch with HF, which is selective towardsthe thin nitride layer underneath. This does not damage the highly dopedFG 36. The thin nitride layer protects the STI oxide 14 during the HFetch. Only thereafter is the thin nitride layer removed, e.g. byetching, which takes much less time in view of the smaller thickness ofthe nitride layer, and therefore is less damaging to the FG material.

Another way to prevent problems with the wet etch is to carry out theimplantation of the FG polysilicon 36 only after wet removal of thenitride of the floating gate separator 32.

After removing the floating gate separator 32, e.g. nitride or oxide andnitride, an interpoly dielectric (IPD) 38 is formed, see FIG. 7. The IPD38 preferably comprises a plurality of insulating materials, e.g. anOxide Nitride Oxide (ONO) layer, and may be formed or grown byconventional techniques. An ONO layer preferably comprises successivelayers of silicon dioxide, silicon nitride and silicon dioxide. Thetotal dielectric thickness of the ONO layer generally is between about10 to 50 nm.

After forming the IPD layer 38, CG polysilicon 40 is deposited(preferably in situ doped), as shown in FIG. 7. The deposition of the CGpolysilicon layer 40 may be done by LPCVD procedures, to a thicknessbetween about 50 to 400 nm. Doping of the CG polysilicon layer 40 iseither accomplished in situ, during deposition, via the addition of asuitable dopant impurity such as arsine or phosphine to a silaneambient, or via an ion implantation procedure, using such a dopant, e.g.arsenic, phosphorous or boron ions applied to an intrinsicallypolysilicon layer.

In a last step in the formation of a NVM according to the presentinvention, CG polysilicon 40 is patterned and etched. This forms theword lines of the memory, which can be seen in the cross sectionperpendicular to the one shown in FIG. 7. This is shown in FIG. 8.

Cell formation is finalized with processing as known by a person skilledin the art (e.g. MDD, spacers, HDD, source/drain formation,silicidation, contact, metalisation etc.—not represented in thedrawings).

According to another embodiment of the present invention, spacers 44 canbe formed next to the floating gate separator 32, e.g. nitride lines.There is started from FIG. 4, previous process steps being the same asfor the first embodiment. Forming of spacers 44 can be done e.g. bydeposition of a thin nitride layer and performing an anisotropic spaceretch. Attentively, an other material can be used. This material,however, should be removable after FG 36 formation. The result afterformation of the spacers is shown in FIG. 9.

Thereafter, FG polysilicon 34 is applied, and it is planarized by CMP asexplained above for the first embodiment. The polysilicon-CMP stops onthe top layer of the floating gate separator 32, and the result is shownin FIG. 10. FGs 36 have been formed.

The next step is the removal of the floating gate separator 32, e.g.nitride, and the spacers 44. This can be done e.g. with a wet etch(H₃PO₄ acid). If the spacers 44 are made of the same material as thefloating gate separator 32, e.g. nitride, they will also be removed inthe same etching step. If the FG polysilicon is highly doped, thenitride etch might slightly attack the FG polysilicon. This can besolved by implanting the FG polysilicon after nitride removal (soundoped polysilicon is used for FG deposition). Applying a dry etch isdifficult, because this tends to be more anisotropic, and tends to notcompletely remove the spacers 44.

If the spacers 44 are made of a material which is different from thematerial of the floating gate separator 32, e.g. the spacer 44 materialis oxide and the floating gate separator 32 material is nitride, thenitride can be removed with a dry etch. The oxide spacers 44 can then beremoved by a HF etch. This HF etch also partly etches the STI oxide 14,but this is not a major problem. In fact, some loss of STI oxide can beadvantageous, because the IPD layer 38 to be formed later on will thenbe below the FG polysilicon 36, and increased coupling between FG 36 andCG 40will be obtained.

After removal of the floating gate separator 32, e.g. nitride, and thespacers 44, a sharp polysilicon tip 46 is obtained in the FG 36. With asharp tip 46 is meant that tangents to the upper, flat surface of the FG36, and the portion of the upstanding wall of the FG 36 where it isadjacent the upper surface, include an angle of less than 90 degrees,preferably less than 70 degrees, still more preferred less than 50degrees. The IPD 38 is then formed. This IPD 38 can be formed e.g. by(CVD) deposition, which follows the shape of the FG polysilicon 36. Forthe IPD 38, e.g. oxide-nitride-oxide (ONO) can be used. A disadvantageof ONO can be the trapping of the charge in the nitride layer whichlowers the erase efficiency. The IPD 38 can also be formed by thermaloxidation or by a combination of a thermal oxidation and an oxidedeposition. A thermal oxidation will make the polysilicon tip 46 evensharper, and improves the field amplification. This sharp tip 46 can beadvantageous in a cell concept where poly-poly erase is used. A commonerase method for non-volatile memories is Fowler-Nordheim tunelling.This method needs relatively high voltages, which do not scale withtransistor dimensions. Another way of erasing is with poly-poly erase,which allows scalability and lower voltages. Especially with a sharp tip46 between the FG 36 and the CG 40, the erase efficiency is increased.The sharp tip 46 produces a high electric field between FG 36 and CG 40during erasing.

On top of the IPD 38 a CG polysilicon 40 is deposited. The resultthereof is shown in FIG. 11.

After the CG polysihcon 40 deposition, the word lines (FG/CG stack) arepatterned, and the rest of the transistor can be processed, as known bya person skilled in the art.

In FIG. 8, the result for the stacked gate concept is shown (1transistor cell). Of course, according to yet another embodiment of thepresent invention, a 2 transistor cell can also be processed (like thepolysihcon-CMP cell concept as explained in WO 01/67517). If the splitgate concept is used instead of stacked gate concept, a sharppolysilicon tip is formed in both bit line and word line directions. Thecross sections in the word line direction are the same as the ones shownin FIG. 3, FIG. 4, FIG. 9, FIG. 10 and FIG. 11. In the bitlinedirection, the result after etching of layer 22 of sacrificial floatinggate material and spacer 44 formation is shown in FIG. 12.

After FG polysilicon deposition and CMP and removal of floating gateseparator 32 and spacers 44, the IPD 38 is formed. Also in this case ONOcan be used, but then the gate dielectric of the select gate (or controlgate) consists of ONO. In this case, a thermal oxidation to form thedielectric isolation on the FG 36 and the gate dielectric is preferred.Due to the high doping level of the FG 36, the oxidation thereof isfaster than the oxidation of the silicon substrate 10, and a thickeroxide is formed on the FG 36 than on the surface 12 of the siliconsubstrate 10. A thermal oxidation will make the polysilicon tip 46 evensharper, which improves field amplification. Also a combination ofthermal oxide and oxide deposition can be used.

FIG. 13 shows a cross-section in the bit line direction of the resultafter complete processing (no HDD spacers) of a split-gate cell.

It is to be understood that although preferred embodiments, specificconstructions and configurations, as well as materials, have beendiscussed herein for devices according to the present invention, variouschanges or modifications in form and detail may be made withoutdeparting from the scope and spirit of this invention.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any 30 reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of other elements orsteps than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.

1. Method for manufacturing an array of semiconductor devices on asubstrate, each device having a floating gate, comprising: first formingisolation zones in the substrate, thereafter forming a floating gateseparator on the isolation zones at locations where separations betweenadjacent floating gates are to be formed, after forming the floatinggate separator, forming the floating gates on the substrate betweenparts of the floating gate separator, and thereafter removing thefloating gate separator so as to obtain slits in between neighboringfloating gates.
 2. Method according to claim 1, furthermore comprising,after forming of the floating gate separator and before forming of thefloating gate, reducing the dimensions of the floating gate separator.3. Method according to claim 2, wherein the dimensions of the floatinggate separator are reduced to sub-lithographic dimensions.
 4. Methodaccording to claim 3, wherein the dimensions of the floating gateseparator are reduced to between 100 nm and 40 nm.
 5. Method accordingto claim 2, wherein the dimensions of the floating gate separator arereduced by resist shrink.
 6. Method according to claim 2, wherein thedimensions of the floating gate separator are reduced by trim plasmaetching.
 7. Method according to claim 2, wherein the dimensions of thefloating gate separator are reduced by an isotropic over-etch of thefloating gate separator.
 8. Method according to claim 2, wherein thedimensions of the floating gate separator are reduced by phase-shiftlithography.
 9. Method according to claim 2, wherein the floating gateseparator comprises nitride material.
 10. Method according to claim 2,wherein the floating gate separator comprises at least two layers ofdifferent material.
 11. Method according to claim 2, furthermorecomprising forming spacers next to the floating gate separator beforeforming the floating gates.
 12. An array of semiconductor devices with afloating-gate to control-gate coupling ratio, comprising: a substratewith a planar surface, an isolation zone in the substrate in the planarsurface, at least two floating gates extending on the substrate in afirst direction, each floating gate partially overlapping the isolationzone and comprising floating gate material, a slit between the twofloating gates, and a control gate extending laterally with respect tothe planar surface over the floating gates, wherein at least one of thefloating gates is provided with a sharp tip of floating gate materialboth in the first direction and in a second direction including an anglewith the first direction.
 13. Array of semiconductor devices accordingto claim 12, wherein the slit is a sub-lithographically dimensionedslit.
 14. Array of semiconductor devices according to claim 12, whereinat least one of the floating gates has a flat top surface.
 15. Array ofsemiconductor devices according to claim 13, wherein at least one of thefloating gates has a flat top surface.